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2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK944
FEATURES
Operating frequency: 7.0 GHz Broadband random jitter: 50 fs rms On-chip input terminations Power supply (VCC - VEE): 2.5 V to 3.3 V
FUNCTIONAL BLOCK DIAGRAM
ADCLK944
LVPECL Q0 VREF Q0 REFERENCE Q1 VT CLK Q2 CLK Q3 Q3
08770-001
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation
Q1 Q2
Figure 1.
GENERAL DESCRIPTION
The ADCLK944 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100 on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.
The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The ECL output stages are designed to directly drive 800 mV each side into 50 terminated to VCC - 2 V for a total differential output swing of 1.6 V. The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
ADCLK944 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Clock Inputs and Outputs ........................................................... 3 Timing Characteristics ................................................................ 3 Power .............................................................................................. 4 Absolute Maximum Ratings............................................................ 5 Determining Junction Temperature .......................................... 5 ESD Caution...................................................................................5 Thermal Performance ...................................................................5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics ..............................................7 Theory of Operation .........................................................................9 Clock Inputs ...................................................................................9 Clock Outputs ................................................................................9 PCB Layout Considerations ...................................................... 10 Input Termination Options ....................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
3/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCLK944 SPECIFICATIONS
Typical values are given for VCC - VEE = 3.3 V and TA = 25C, unless otherwise noted. Minimum and maximum values are given for the full VCC - VEE = 3.3 V + 10% to 2.5 V - 5% and TA = -40C to +85C variation, unless otherwise noted.
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter DC INPUT CHARACTERISTICS Input Common-Mode Voltage Input Differential Voltage Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage, Single-Ended Voltage Reference Output Voltage Output Resistance Symbol VICM VID CIN RIN Min VEE + 1.35 0.4 0.4 50 100 50 20 VOH VOL VO VREF VCC - 1.26 VCC - 1.99 600 (VCC + 1)/2 250 VCC - 0.76 VCC - 1.54 960 Typ Max VCC - 0.1 3.4 Unit V V p-p pF k A V V mV V Test Conditions/Comments
1.7 V between input pins
VT open
Load = 50 to (VCC - 2.0 V) Load = 50 to (VCC - 2.0 V) VOH - VOL, output static -500 A to +500 A
TIMING CHARACTERISTICS
Table 2.
Parameter AC PERFORMANCE Maximum Output Frequency Output Rise/Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew 1 Part-to-Part Skew Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 2 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise fIN = 1 GHz Symbol Min 6.2 tR tPD 35 70 Typ 7.0 50 100 75 75 130 15 35 26 50 Max Unit GHz ps ps fs/C ps ps fs rms fs rms Test Conditions/Comments Differential output voltage swing > 0.8 V (see Figure 4) 20% to 80%, measured differentially VID = 1.6 V p-p
VID = 1.6 V p-p BW = 12 kHz to 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V Input slew rate > 1 V/ns (see Figure 11) 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset >1 MHz offset
-118 -135 -144 -150 -150
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
1 2
The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
Rev. 0 | Page 3 of 12
ADCLK944
POWER
Table 3.
Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2
1 2
Symbol VCC - VEE IVEE IVEE IVCC IVCC PSRVCC PSRVCC
Min 2.375
Typ
Max 3.63
Unit V mA mA mA mA ps/V dB
Test Conditions/Comments 3.3 V + 10% to 2.5 V - 5% Static VCC - VEE = 2.5 V 5% VCC - VEE = 3.3 V 10% VCC - VEE = 2.5 V 5% VCC - VEE = 3.3 V 10%
35 37 139 138 -3 28
49 165
Change in tPD per change in VCC. Change in output swing per change in VCC.
Rev. 0 | Page 4 of 12
ADCLK944 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage VCC - VEE Input Voltage CLK, CLK CLK to CLK Input Termination, VT to CLK, CLK Input Current, CLK, CLK to VT Pin (CML, LVPECL Termination) Maximum Voltage on Output Pins Maximum Output Current Voltage Reference (VREF) Operating Temperature Ambient Range Junction Storage Temperature Range Rating 6.0 V VEE - 0.5 V to VCC + 0.5 V 1.8 V 2 V 40 mA VCC + 0.5 V 35 mA VCC to VEE -40C to +85C 150C -65C to +150C
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application printed circuit board (PCB), use the following equation: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is as indicated in Table 5. PD is the power dissipation. Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ using the following equation: TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JB are provided in Table 5 for package comparison and PCB design considerations.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter Junction-to-Ambient Thermal Resistance Still Air 0.0 m/sec Airflow Moving Air 1.0 m/sec Airflow 2.5 m/sec Airflow Junction-to-Board Thermal Resistance Moving Air 1.0 m/sec Airflow Junction-to-Case Thermal Resistance (Die-to-Heat Sink) Still Air 0.0 m/sec Airflow Junction-to-Top-of-Package Characterization Parameter Still Air 0.0 m/sec Airflow
1
Symbol JA JMA
Description Per JEDEC JESD51-2
Value 1
Unit
78 Per JEDEC JESD51-6 68 61 JB Per JEDEC JESD51-8 49 JC Per MIL-STD-883, Method 1012.1 1.5 JT Per JEDEC JESD51-2 2.0
C/W C/W C/W
C/W
C/W
C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 5 of 12
ADCLK944 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 Q0 14 Q0 13 VCC 16 VEE
CLK 1 VT 2 VREF 3 CLK 4
12 Q1
ADCLK944
TOP VIEW (Not to Scale)
11 Q1 10 Q2 9 Q2
NOTES 1. EXPOSED PAD MUST BE CONNECTED TO VEE.
VCC 8
VEE 5
Q3 6
Q3 7
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5, 16 6, 7 8, 13 9, 10 11, 12 14, 15 Mnemonic CLK VT VREF CLK VEE Q3, Q3 VCC Q2, Q2 Q1, Q1 Q0, Q0 EPAD Description Differential Input (Positive). Center Tap. This pin provides the center tap of a 100 input resistor for the CLK and CLK inputs. Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs. Differential Input (Negative). Negative Supply Pin. Differential LVPECL Outputs. Positive Supply Pin. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. The exposed pad must be connected to VEE.
Rev. 0 | Page 6 of 12
08770-002
ADCLK944 TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25C, clock outputs terminated at 50 to VCC - 2 V, unless otherwise noted.
1
1
08770-003
CH1 300mV
M 1.25ns 20.0GS/s A CH1 36.0mV
IT 25.0ps/pt
CH1 300mV
M 250ps 20.0GS/s A CH1 36.0mV
IT 5.0ps/pt
Figure 3. LVPECL Differential Output Waveform at 200 MHz
Figure 6. LVPECL Differential Output Waveform at 1000 MHz
1.6
1.55
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
1.4 3.3V 1.2 2.5V 1.0 0.8 0.6 0.4 0.2 0 0 1000 2000 3000 4000 5000 6000 7000 8000 FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
+25C 1.50
+85C -40C
1.45
1.40
1.35
08770-004
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
POWER SUPPLY VOLTAGE (V)
Figure 4. Differential Output Voltage Swing vs. Frequency
Figure 7. Differential Output Voltage Swing vs. Power Supply Voltage and Temperature, VID = 1.6 V p-p
140
80 85
130
PROPAGATION DELAY (ps)
PROPAGATION DELAY (ps)
90 DELAY 3.3V 95
120
110 2.5V 100 3.3V 90
100 105 DELAY 2.5V 110
08770-005
0.3 0.5 0.7 0.9 DIFFERENTIAL INPUT VOLTAGE SWING (V)
1.1
1.5 2.0 2.5 3.0 DC COMMON-MODE VOLTAGE (VICM - VEE)
3.5
Figure 5. Propagation Delay vs. Differential Input Voltage Swing
Figure 8. Propagation Delay vs. DC Common-Mode Voltage
Rev. 0 | Page 7 of 12
08770-008
115 0.1
80 1.0
08770-009
1.30 2.2
08770-006
ADCLK944
160 140
300
250
RANDOM JITTER (fs rms)
08770-010
120
IVCC -40C +25C +85C
CURRENT (mA)
200
100 80 60 40 IVEE 20 0 2.375 2.500 2.625 2.970
150
100
50
3.300
3.630
0
5
10 INPUT SLEW RATE (V/ns)
15
20
POWER SUPPLY VOLTAGE (V)
Figure 9. Power Supply Current vs. Power Supply Voltage and Temperature, All Outputs Loaded (50 to VCC - 2 V)
-90 -100 -110 -120 -130 -140 -150 -160 -170 10
Figure 11. Random Jitter vs. Input Slew Rate, VID Method
PHASE NOISE (dBc/Hz)
ADCLK944
CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M
08770-011
FREQUENCY OFFSET (Hz)
Figure 10. Absolute Phase Noise Measured at 1 GHz with Agilent E5052B
Rev. 0 | Page 8 of 12
08770-012
0
ADCLK944 THEORY OF OPERATION
CLOCK INPUTS
The ADCLK944 accepts a differential clock input and distributes it to all four LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). The device has a differential input equipped with center-tapped, differential, 100 on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended, 3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs (see Figure 20 and Figure 21). Maintain the differential input voltage swing from approximately 400 mV p-p to no more than 3.4 V p-p. See Figure 18 through Figure 21 for various clock input termination schemes. Output jitter performance is significantly degraded by an input slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. Figure 13 through Figure 16 depict various LVPECL output termination schemes. When dc-coupled, VCC of the receiving buffer should match VS_DRV.
VS_DRV
ADCLK944
Z0 = 50 VCC - 2V
VCC = VS_DRV
50 LVPECL
08770-014
50 Z0 = 50
Figure 13. DC-Coupled, 3.3 V LVPECL
Thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK944 should equal VCC of the receiving buffer. Although the resistor combination shown in Figure 14 results in a dc bias point of VS_DRV - 2 V, the actual common-mode voltage is VS_DRV - 1.3 V because there is additional current flowing from the ADCLK944 LVPECL driver through the pull-down resistor.
VS_DRV VS_DRV
ADCLK944
50 SINGLE-ENDED (NOT COUPLED) 50 127 127
VCC
LVPECL
CLOCK OUTPUTS
The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK944 are designed to directly drive 800 mV into a 50 cable or into microstrip/stripline transmission lines terminated with 50 referenced to VCC - 2 V, as shown in Figure 13. The LVPECL output stage is shown in Figure 12. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse-width-dependent propagation delay dispersion.
VCC
Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
LVPECL Y-termination (see Figure 15) is an elegant termination scheme that uses the fewest components and offers both oddand even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitterfollower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue.
VS_DRV
ADCLK944
Z0 = 50 50 Z0 = 50
VCC = VS_DRV
50 LVPECL
08770-016
50
Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination
Q Q
VS_DRV
ADCLK944
0.1nF 100 DIFFERENTIAL 100 (COUPLED) 0.1nF TRANSMISSION LINE
VCC
LVPECL
08770-013
Figure 12. Simplified Schematic Diagram of the LVPECL Output Stage
Figure 16. AC-Coupled LVPECL with Parallel Transmission Line
Rev. 0 | Page 9 of 12
08770-017
VEE
200
200
08770-015
83
83
ADCLK944
PCB LAYOUT CONSIDERATIONS
The ADCLK944 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to the ground plane assume that the VEE power plane is grounded for LVPECL operation. Note that, for ECL operation, the VCC power plane becomes the ground plane. It is also important to adequately bypass the input and output supplies. Place a 1 F electrolytic bypass capacitor within several inches of each VCC power supply pin to the ground plane. In addition, place multiple high quality 0.001 F bypass capacitors as close as possible to each VCC supply pin, and connect the capacitors to the ground plane with redundant vias. Select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines; such discontinuities can affect jitter performance. In a 50 environment, input and output matching have a significant impact on performance. The buffer provides internal 50 termination resistors for both the CLK and CLK inputs. Normally, the return side is connected to the reference pin that is provided. Bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are dccoupled to a source, take care to ensure that the pins are within the rated input differential and common-mode voltage ranges. If the return is floated, the device exhibits a 100 cross-termination, but the source must then control the common-mode voltage and supply the input bias currents. ESD/clamp diodes between the input pins prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK944 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE pins. When properly mounted, the ADCLK944 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK944. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer of the PCB down to the VEE power plane (see Figure 17). The ADCLK944 evaluation board (ADCLK944/PCBZ) provides an example of how to attach the part to the PCB.
VIAS TO VEE POWER PLANE
Figure 17. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 10 of 12
08770-018
ADCLK944
INPUT TERMINATION OPTIONS
VCC VREF VT 50 CLK CLK 50
VREF VT 50 CLK CLK 50
08770-019
CONNECT VT TO VCC.
CONNECT VT TO VREF .
Figure 18. Interfacing to CML Inputs
Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS
VREF VT
VREF VT VCC - 2V 50 CLK CLK 50
50 CLK CLK
50
Figure 19. Interfacing to PECL Inputs
Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs
Rev. 0 | Page 11 of 12
08770-022
CONNECT VT TO VCC - 2V.
CONNECT VT, VREF , AND CLK TOGETHER. PLACE A BYPASS CAPACITOR FROM VT TO GROUND. ALTERNATIVELY, VT, VREF , AND CLK CAN BE CONNECTED TOGETHER, GIVING A CLEANER LAYOUT AND A 180 PHASE SHIFT.
08770-020
08770-021
ADCLK944 OUTLINE DIMENSIONS
PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.50 BSC 0.30 0.25 0.18
13 12 EXPOSED PAD 16 1
PIN 1 INDICATOR
1.60 1.50 SQ 1.40
4 5
9
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
8
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-18) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADCLK944BCPZ-R2 ADCLK944BCPZ-R7 ADCLK944BCPZ-WP ADCLK944/PCBZ
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ Evaluation Board
Package Option CP-16-18 CP-16-18 CP-16-18
111808-A
Branding Code Y2K Y2K Y2K
Z = RoHS Compliant Part.
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08770-0-3/10(0)
Rev. 0 | Page 12 of 12

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